VLSI 2010 Annual Symposium

1. Intelligent NOC Hotspot Prediction
Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides

2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model
Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

3. Trust Management Through Hardware Means: Design Concerns and Optimizations
Apostolos P. Fournaris, Daniel M. Hein

4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures
Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martinez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Fan Dongrui, Zhang Hao, Tang Shibin

5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures
C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Biagio, E. Speziale, M. Tartara, D. Melpignano, J.-M. Zins, D. Siorpaes, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers, H. Meyr, J. Ansari, P. Mähönen, B. Vanthournout

6. Adaptive Task Migration Policies for Thermal Control in MPSoCs
David Cuesta, Jose Ayala, Jose Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii

7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
Sotirios Xydis, Kiamal Pekmestzi, Dimitrios Soudris, George Economakos

8. A Scalable Bandwidth-Aware Architecture for Connected Component Labeling
Vikram Sampath Kumar, Kevin Irick, Ahmed Al Maashri, Vijaykrishnan Narayanan

9. The SATURN Approach to SysML-Based HW/SW Codesign
Wolfgang Mueller, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda

10. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
Christos Baloukas, Lazaros Papadopoulos, Dimitrios Soudris, Sander Stuijk, Olivera Jovanovic, Florian Schmoll, Peter Marwedel, Daniel Cordes, Robert Pyka, Arindam Mallik, Stylianos Mamagkakis, François Capman, Séverin Collet, Nikolaos Mitas, Dimitrios Kritharidis

11. The MOSART Mapping Optimization for Multi-Core ARchiTectures
Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrja, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin

12. XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluation
Theodoros Lioris, Grigoris Dimitroulakos, Kostas Masselos

13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing
Vasileios Tenentes, Xrysovalantis Kavousianos

14. SUT-RNS Forward and Reverse Converters
E. Vassalos, D. Bakalis, H. T. Vergos

15. Off-Chip SDRAM Access Through Spidergon STNoC
Khaldon Hassan, Marcello Coppola

16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Krishnendu Chakrabarty, Yang Zhao

17. FPGA Startup Through Sequential Partial and Dynamic Reconfiguration
Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker

18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware
Lars Braun, Jürgen Becker

19. Design for Embedded Reconfigurable Systems Using MORPHEUS Platform
Paul Brelet, Philippe Millet, Arnaud Grasset, Philippe Bonnot, Frank Ieromnimon, Dimitrios Kritharidis, Nikolaos S. Voros

20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach
Diana Göhringer, Jürgen Becker

Nyckelord: Engineering, Circuits and Systems, Computer Systems Organization and Communication Networks, Register-Transfer-Level Implementation, Performance and Reliability, Computational Biology/Bioinformatics, Electronics and Microelectronics, Instrumentation