Churiwala, Sanjay
Principles of VLSI RTL Design
Table of contents
1. Introduction to VLSI RTL Designs
Sanjay Churiwala, Sapan Garg
2. Ensuring RTL Intent
Sanjay Churiwala, Sapan Garg
3. Timing Analysis
Sanjay Churiwala, Sapan Garg
4. Clock Domain Crossing (CDC)
Sanjay Churiwala, Sapan Garg
5. Power
Sanjay Churiwala, Sapan Garg
6. Design for Test (DFT)
Sanjay Churiwala, Sapan Garg
7. Timing Exceptions
Sanjay Churiwala, Sapan Garg
8. Congestion
Sanjay Churiwala, Sapan Garg
Nyckelord: Engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design
- Författare
- Churiwala, Sanjay
- Garg, Sapan
- Utgivare
- Springer
- Utgivningsår
- 2011
- Språk
- en
- Utgåva
- 1
- Sidantal
- 15 sidor
- Kategori
- Teknologi, energi, trafik
- Format
- E-bok
- eISBN (PDF)
- 9781441992963
