Low-Power High-Speed ADCs for Nanometer CMOS Integration

1. Introduction

2. A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS

3. A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS

4. A 0.4 ps-RMS-Jitter 1–3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification

5. Conclusions and Future Directions

DRM-restrictions

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Nyckelord: TECHNOLOGY & ENGINEERING / General TEC000000