Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

2. Introduction
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

3. High-Level Synthesis Fundamentals
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

4. Power Modeling and Estimation at Transistor and Logic Gate Levels
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

5. Architectural Power Modeling and Estimation
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

6. Power Reduction Fundamentals
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

7. Energy or Average Power Reduction
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

8. Peak Power Reduction
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

9. Transient Power Reduction
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

10. Leakage Power Reduction
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

11. Conclusions and Future Direction
Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyadarsan Patra

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