Modern Circuit Placement

1.Benchmarks

1. ISPD 2005/2006 Placement Benchmarks
Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia

2. Locality and Utilization in Placement Suboptimality
Jason Cong, Michalis Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie

2.Flat Placement Techniques

3. DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective
Tao Luo, David Z. Pan

4. Kraftwerk: A Fast and Robust Quadratic Placer Using an Exact Linear Net Model
Peter Spindler, Frank M. Johannes

3.Top-Down Partitioning-Based Techniques

5. Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability
Jarrod A. Roy, David A. Papa, Igor L. Markov

6. Congestion Minimization in Modern Placement Circuits
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh

4.Multilevel Placement Techniques

7. APlace: A High Quality, Large-Scale Analytical Placer
Andrew B. Kahng, Sherief Reda, Qinke Wang

8. FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm
Natarajan Viswanathan, Min Pan, Chris Chu

9. mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement
Bo Hu, Malgorzata Marek-Sadowska

10. mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control
Tony F. Chan, Kenton Sze, Joseph R. Shinnerl, Min Xie

11. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang

12. Conclusion and Challenges

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