Davidmann, Simon
SystemVerilog for Design
Table of contents
1. Introduction to SystemVerilog
2. SystemVerilog Declaration Spaces
3. SystemVerilog Literal Values and Built-in Data Types
4. SystemVerilog User-Defined and Enumerated Types
5. SystemVerilog Arrays, Structures and Unions
6. SystemVerilog Procedural Blocks, Tasks and Functions
7. SystemVerilog Procedural Statements
8. Modeling Finite State Machines with SystemVerilog
9. SystemVerilog Design Hierarchy
10. SystemVerilog Interfaces
11. A Complete Design Modeled with SystemVerilog
12. Behavioral and Transaction Level Modeling
DRM-restrictions
Printing: not available
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Nyckelord: TECHNOLOGY & ENGINEERING / General TEC000000
- Författare
- Davidmann, Simon
- Flake, Peter
- Sutherland, Stuart
- Utgivare
- Springer
- Utgivningsår
- 2006
- Språk
- en
- Utgåva
- 1
- Kategori
- Teknologi, energi, trafik
- Format
- E-bok
- eISBN (PDF)
- 9780387364957
