Bergeron, Janick
Writing Testbenches using System Verilog
Table of contents
1. What is Verification?
2. Verification Technologies
3. The Verification Plan
4. High-Level Modeling
5. Stimulus and Response
6. Architecting Testbenches
7. Simulation Management
DRM-restrictions
Printing: not available
Clipboard copying: not available
Nyckelord: TECHNOLOGY & ENGINEERING / General TEC000000
- Författare
- Bergeron, Janick
- Utgivare
- Springer
- Utgivningsår
- 2006
- Språk
- en
- Utgåva
- 1
- Kategori
- Teknologi, energi, trafik
- Format
- E-bok
- eISBN (PDF)
- 9780387312750
