Network-on-Chip Architectures

1. Introduction
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

2. A Baseline NoC Architecture
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

3. ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

4. RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

5. Exploring FaultoTolerant Network-on-Chip Architectures [37]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

6. On the Effects of Process Variation in Network-on-Chip Architectures [45]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

7. The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

8. Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

9. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

10. Digest of Additional NoC MACRO-Architectural Research
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

11. Conclusions and Future Work
Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

Avainsanat: Engineering, Circuits and Systems, Processor Architectures