Parasitic Substrate Coupling in High Voltage Integrated Circuits

1. Overview of Parasitic Substrate Coupling
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

2. Design Challenges in High-Voltage ICs
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

3. Substrate Modeling with Parasitic Transistors
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

4. TCAD Validation of the Model
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

5. Extraction Tool for the Substrate Network
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

6. Parasitic Bipolar Transistors in Benchmark Structures
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

7. Substrate Coupling Analysis and Evaluation of Protection Strategies
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

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