From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators

1. Introduction
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

Part I. Predicting and Preventing Errors

2. Instruction-Level Tolerance
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

3. Sequence-Level Tolerance
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

4. Procedure-Level Tolerance
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

5. Kernel-Level Tolerance
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

6. Hierarchically Focused Guardbanding
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

Part II. Detecting and Correcting Errors

7. Work-Unit Tolerance
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

8. Memristive-Based Associative Memory for Error Recovery
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

Part III. Accepting Errors

9. Accuracy-Configurable OpenMP
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

10. An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

11. Memristive-Based Associative Memory for Approximate Computational Reuse
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

12. Spatial and Temporal Memoization
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

13. Outlook
Abbas Rahimi, Luca Benini, Rajesh K. Gupta

Avainsanat: Engineering, Circuits and Systems, Processor Architectures, Logic Design