Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

1. Introduction
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

2. Related Work
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

3. Background
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

4. Architectural Selection Using High Level Synthesis
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

5. Statistical Regression Based Power Models
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

6. Coprocessor Design Space Exploration Using High Level Synthesis
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

7. Regression-Based Dynamic Power Estimation for FPGAs
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

8. High Level Simulation Directed RTL Power Estimation
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

9. Applying Verification Collaterals for Accurate Power Estimation
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

10. Power Reduction Using High-Level Clock-Gating
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

11. Model-Checking to Exploit Sequential Clock-Gating
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

12. System Level Simulation Guided Approach for Clock-Gating
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

13. Conclusions
Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

Avainsanat: Engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design