Low Power Networks-on-Chip

1. Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections
Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar

2. Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano

3. Adaptive Voltage Control for Energy-Efficient NoC Links
Paul Ampadu, Bo Fu, David Wolpert, Qiaoyan Yu

4. Asynchronous Communications for NoCs
Stanislavs Golubcovs, Alex Yakovlev

5. Application-Specific Routing Algorithms for Low Power Network on Chip Design
Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania

6. Adaptive Data Compression for Low-Power On-Chip Networks
Yuho Jin, Ki Hwan Yum, Eun Jung Kim

7. Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study
Rudy Beraha, Isask’har Walter, Israel Cidon, Avinoam Kolodny

8. Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli

9. CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study
Jung Ho Ahn, Raymond G. Beausoleil, Nathan Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease

10. RF-Interconnect for Future Network-On-Chip
Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman

Avainsanat: Engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design