Interconnect-Centric Design for Advanced SoC and NoC

I.Physical and Electrical Issues

1. System-on-Chip-Challenges in the Deep-Sub-Micron Era
Jan M. Rabaey

2. Wires as Interconnects
Li-Rong Zheng, Hannu Tenhunen

3. Global Interconnect Analysis
Tero Nurmi, Jian Liu, Dinesh Pamunuwa, Tapani Ahonen, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen

4. Design Methodologies for on-Chip Inductive Interconnect
Magdy A. El-Moursy, Eby G. Friedman

5. Clock Distribution for High Performance Designs
Stefan Rusu

II.Logical and Architectural Issues

6. Error-Tolerant Interconnect Schemes
Heiko Zimmer, Axel Jantsch

7. Power Reduction Coding for Buses
Paul P. Sotiriadis

8. Bus Structures in Network-on-Chips
Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen

9. From Buses to Networks
David Sigüuenza-Tortosa, Jari Nurmi

10. Arbitration and Routing Schemes for on-Chip Packet Networks
Heikki Kariniemi, Jari Nurmi

III.Design Methodology and Tools

11. Self-Timed Approach for Noise Reduction in NoC Reduction in NoC
Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila, Jouni Isoaho

12. Formal Communication Modeling and Refinement
Juha Plosila, Tiberiu Seceleanu, Kaisa Sere

13. Network-Centric System-Level Model for Multiprocessor Soc Simulation
Jan Madsen, 1Shankar Mahadevan, Kashif Virk

14. Socket-Based Design Using Decoupled Interconnects
Drew Wingard

IV.Application Cases

15. Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV
Kees Goossens, Om Prakash Gangwal, Jens Röover, A.P. Niranjan

16. A Brunch from the Coffee Table-Case Study in NoC Platform Design
Tapani Ahonen, Seppo Virtanen, Juha Kylliäainen, Dragos Truscan, Tuukka Kasanko, David Sigäuenza-Tortosa, Tapio Ristimäaki, Jani Paakkulainen, Tero Nurmi, Ilkka Saastamoinen, Hannu Isäannäainen, Johan Lilius, Jari Nurmi, Jouni Isoaho

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Avainsanat: TECHNOLOGY & ENGINEERING / General TEC000000