Sapatnekar, Sachin S.
Routing Congestion in VLSI Circuits: Estimation and Optimization
Table of contents
Part I.The Origins of Congestion
1. An Introduction to Routing Congestion
Part II.The Estimation of Congestion
2. Placement-level Metrics for Routing Congestion
3. Synthesis-level Metrics for Routing Congestion
Part III.The Optimization of Congestion
4. Congestion Optimization During Interconnect Synthesis and Routing
5. Congestion Optimization During Placement
6. Congestion Optimization During Technology Mapping and Logic Synthesis
7. Congestion Implications of High Level Design
DRM-restrictions
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Avainsanat: TECHNOLOGY & ENGINEERING / General TEC000000
- Tekijä(t)
- Sapatnekar, Sachin S.
- Saxena, Prashant
- Shelar, Rupesh S.
- Julkaisija
- Springer
- Julkaisuvuosi
- 2007
- Kieli
- en
- Painos
- 1
- Kategoria
- Tekniikka, energia, liikenne
- Tiedostomuoto
- E-kirja
- eISBN (PDF)
- 9780387485508
