The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits

1. Sizing the Intrinsic Gain Stage
Paul G. A. Jespers

2. The Charge Sheet Model Revisited
Paul G. A. Jespers

3. Graphical Interpretation of the Charge Sheet Model
Paul G. A. Jespers

4. Compact Modeling
Paul G. A. Jespers

5. The Real Transistor
Paul G. A. Jespers

6. The Real Intrinsic Gain Stage
Paul G. A. Jespers

7. The Common-Gate Configuration
Paul G. A. Jespers

8. Sizing the Miller Op. Amp.
Paul G. A. Jespers

Avainsanat: Engineering, Circuits and Systems, Processor Architectures, Solid State Physics, Spectroscopy and Microscopy