Introduction to Advanced System-on-Chip Test Design and Optimization

Part 1.Testing Concepts

1. Introduction
2. Design Flow
3. Design for Test
4. Boundary Scan
Part 2.SOC Design for Testability

5. System Modeling
6. Test Conflicts
7. Test Power Dissipation
8. Test Access Mechanism
9. Test Scheduling
Part 3.SOC Test Applications

10. A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
11. An Integrated Framework for the Design and Optimization of SOC Test Solutions
12. Efficient Test Solutions for Core-Based Designs
13. Core Selection in the SOC Test Design-Flow
14. Defect-Aware Test Scheduling
15. An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint

DRM-restrictions

Printing: not available
Clipboard copying: not available

Avainsanat: TECHNOLOGY & ENGINEERING / General TEC000000