Amara, Amara

Emerging Technologies and Circuits

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Table of contents

1. Synergy Between Design and Technology: A Key Factor in the Evolving Microelectronic Landscape
Michel Brillouët

2. New State Variable Opportunities Beyond CMOS: A System Perspective
Victor V. Zhirnov, Ralph K. Cavin, George I. Bourianoff

3. A Simple Compact Model to Analyze the Impact of Ballistic and Quasi-Ballistic Transport on Ring Oscillator Performance
S. Martinie, D. Munteanu, G. Carval, J. L. Autran

4. Low-Voltage Scaled 6T FinFET SRAM Cells
N. Collaert, K. Arnim, R. Rooyackers, T. Vandeweyer, A. Mercha, B. Parvais, L. Witters, A. Nackaerts, E. Altamirano Sanchez, M. Demand, A. Hikavyy, S. Demuynck, K. Devriendt, F. Bauer, I. Ferain, A. Veloso, K. Meyer, S. Biesemans, M. Jurczak

5. Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction
Kazuhiko Endo, Shin-ichi O’uchi, Yuki Ishikawa, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Meishoku Masahara, Junichi Tsukada, Kenichi Ishii, Eiichi Suzuki

6. Metal Gate Effects on a 32 nm Metal Gate Resistor
Thuy Dao, Ik_Sung Lim, Larry Connell, Dina H. Triyoso, Youngbog Park, Charlie Mackenzie

7. Threshold Voltage Shift Instability Induced by Plasma Charging Damage in MOSFETS with High-K Dielectric
Koji Eriguchi, Masayuki Kamei, Kenji Okada, Hiroaki Ohta, Kouichi Ono

8. Analysis of SI Substrate Damage Induced by Inductively Coupled Plasma Reactor with Various Superposed Bias Frequencies
Y. Nakakubo, A. Matsuda, M. Kamei, H. Ohta, K. Eriguchi, K. Ono

9. CMOS SOI Technology for WPAN: Application to 60 GHZ LNA
A. Siligaris, C. Mounet, B. Reig, P. Vincent, A. Michel

10. SRAM Memory Cell Leakage Reduction Design Techniques in 65 nm Low Power PD-SOI CMOS
Olivier Thomas, Marc Belleville, Richard Ferrant

11. Resilient Circuits for Dynamic Variation Tolerance
Keith A. Bowman, James W. Tschanz

12. Process Variability-Induced Timing Failures – A Challenge in Nanometer CMOS Low-Power Design
Xiaonan Zhang, Xiaoliang Bai

13. How Does Inverse Temperature Dependence Affect Timing Sign-Off
Sean H. Wu, Alexander Tetelbaum, Li-C. Wang

14. CMOS Logic Gates Leakage Modeling Under Statistical Process Variations
Carmelo D’Agostino, Philippe Flatresse, Edith Beigne, Marc Belleville

15. On-Chip Circuit Technique for Measuring Jitter and Skew with Picosecond Resolution
K. A. Jenkins, Z. Xu, A. P. Jose, K. L. Shepard

16. DC–DC Converter Technologies for On-Chip Distributed Power Supply Systems – 3D Stacking and Hybrid Operation
Makoto Takamiya, Koichi Onizuka, Koichi Ishida, Takayasu Sakurai

17. Sampled Analog Signal Processing: From Software-Defined to Software Radio
François Rivet, André Mariano, Yann Deval, Dominique Dallet, Jean-Baptiste Begueret, Didier Belot

Keywords: Engineering, Circuits and Systems, Nanotechnology, Memory Structures

Publication year
Lecture Notes in Electrical Engineering
Page amount
9 pages
Technology, Energy, Traffic

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