Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

1. Introduction
Brandon Noia, Krishnendu Chakrabarty

2. Wafer Stacking and 3D Memory Test
Brandon Noia, Krishnendu Chakrabarty

3. Built-In Self-Test for TSVs
Brandon Noia, Krishnendu Chakrabarty

4. Pre-bond TSV Test Through TSV Probing
Brandon Noia, Krishnendu Chakrabarty

5. Pre-bond Scan Test Through TSV Probing
Brandon Noia, Krishnendu Chakrabarty

6. Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths
Brandon Noia, Krishnendu Chakrabarty

7. Post-Bond Test Wrappers and Emerging Test Standards
Brandon Noia, Krishnendu Chakrabarty

8. Test-Architecture Optimization and Test Scheduling
Brandon Noia, Krishnendu Chakrabarty

9. Conclusions
Brandon Noia, Krishnendu Chakrabarty

Keywords: Engineering, Circuits and Systems, Processor Architectures, Semiconductors