Designing 2D and 3D Network-on-Chip Architectures

Part I. Network-on-Chip Design Methodology

1. Network-on-Chip Technology: A Paradigm Shift
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

2. NoC Modeling and Topology Exploration
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

3. Communication Architecture
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

4. Power and Thermal Effects and Management
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

5. NoC-Based System Integration
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

6. NoC Verification and Testing
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

7. The Spidergon STNoC
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

8. Middleware Memory Management in NoC
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

9. On Designing 3-D Platforms
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

10. The SYSMANTIC NoC Design and Prototyping Framework
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

Part II. Suggested Projects

11. Projects on Network-on-Chip
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

Keywords: Engineering, Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures