Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

1. Regular Versus Irregular TSV Placement for 3D IC
Sung Kyu Lim

2. Steiner Routing for 3D IC
Sung Kyu Lim

3. Buffer Insertion for 3D IC
Sung Kyu Lim

4. Low Power Clock Routing for 3D IC
Sung Kyu Lim

5. Power Delivery Network Design for 3D IC
Sung Kyu Lim

6. 3D Clock Routing for Pre-bond Testability
Sung Kyu Lim

7. TSV-to-TSV Coupling Analysis and Optimization
Sung Kyu Lim

8. TSV Current Crowding and Power Integrity
Sung Kyu Lim

9. Modeling of Atomic Concentration at the Wire-to-TSV Interface
Sung Kyu Lim

10. Multi-objective Architectural Floorplanning for 3D IC
Sung Kyu Lim

11. Thermal-Aware Gate-Level Placement for 3D IC
Sung Kyu Lim

12. 3D IC Cooling with Micro-Fluidic Channels
Sung Kyu Lim

13. Mechanical Reliability Analysis and Optimization for 3D ICs
Sung Kyu Lim

14. Impact of Mechanical Stress on Timing Variation for 3D IC
Sung Kyu Lim

15. Chip/Package Co-analysis of Mechanical Stress for 3D IC
Sung Kyu Lim

16. 3D Chip/Package Co-analysis of Stress-Induced Timing Variations
Sung Kyu Lim

17. TSV Interfacial Crack Analysis and Optimization
Sung Kyu Lim

18. Ultra High Density Logic Designs Using Monolithic 3D Integration
Sung Kyu Lim

19. Impact of TSV Scaling on 3D IC Design Quality
Sung Kyu Lim

20. 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory
Sung Kyu Lim

Keywords: Engineering, Circuits and Systems, Nanotechnology and Microengineering, Processor Architectures