High-Level Verification

1. Introduction
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

2. Background
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

3. Related Work
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

4. Verification Using Automated Theorem Provers
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

5. Execution-Based Model Checking for High-Level Designs
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

6. Bounded Model Checking for Concurrent Systems: Synchronous Vs. Asynchronous
Malay K. Ganai

7. Translation Validation of High-Level Synthesis
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

8. Parameterized Program Equivalence Checking
Zachary Tatlock

9. Conclusions and Future Work
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta

Keywords: Engineering, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design