Design, Automation, and Test in Europe

1. System Level Design

1. System Level Design: Past, Present, and Future
Daniel D. Gajski

2. Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop

3. EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability
Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil Dutt, Alex Nicolau

4. RTOS Modeling for System Level Design
Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski

5. Context-Aware Performance Analysis for Efficient Embedded System Design
Marek Jersak, Rafik Henia, Rolf Ernst

6. Lock-Free Synchronization for Dynamic Embedded Real-Time Systems
Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen

7. What If You Could Design Tomorrow’s System Today?
Neal Wingen

Part II. Networks on Chip

8. Networks on Chips
Giovanni Micheli

9. A Generic Architecture for On-Chip Packet-Switched Interconnections
Pierre Guerrier, Alain Greiner

10. Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. Meerbergen, P. Wielage, E. Waterlander

11. Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures
Jingcao Hu, Radu Marculescu

12. xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni Micheli

13. A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Michael Storgaard, Jan Madsen, Rasmus Grøndahl Olsen

Part III. Modeling, Simulation and Run-Time Management

14. Modeling, Simulation and Run-Time Management
Enrico Macii

15. Dynamic Power Management for Nonstationary Service Requests
Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni Micheli

16. Quantitative Comparison of Power Management Algorithms
Yung-Hsiang Lu, Eui-Young Chung, Tajana Šimunic, Luca Benini, Giovanni Micheli

17. Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives
Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan, Wim Dehaene

18. Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application
Amith Singhee, Rob A. Rutenbar

19. Compositional Specification of Behavioral Semantics
Kai Chen, Janos Sztipanovits, Sandeep Neema

Part IV. Design Technology for Advanced Digital Systems in CMOS and Beyond

20. Design Technology for Advanced Digital Systems in CMOS and Beyond
Hugo Man, Hugo Man

21. Address Bus Encoding Techniques for System-Level Power Optimization
Luca Benini, Giovanni Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano, Luca Benini, Giovanni Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano

22. MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
Robert P. Dick, Niraj K. Jha, Robert P. Dick, Niraj K. Jha

23. Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processors
Gang Quan, Xiaobo Sharon Hu, Gang Quan, Xiaobo Sharon Hu

24. Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha

5. Physical Design and Validation

25. Physical Design and Validation
Jochen A. G. Jess

26. Interconnect Tuning Strategies for High-Performance ICs
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma

27. Efficient Inductance Extraction via Windowing
Michael Beattie, Lawrence Pileggi

28. Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee

29. A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology
Cristiano Niclass, Maximilian Sergio, Edoardo Charbon

Part VI. Test and Verification

30. The Test and Verification Influential Papers in the 10 Years of DATE
T. W. Williams, R. Kapur

31. Cost Reduction and Evaluation of a Temporary Faults-Detecting Technique
Lorena Anghel, Michael Nicolaidis

32. An Integrated System-on-Chip Test Framework
Erik Larsson, Zebo Peng

33. Efficient Spectral Techniques for Sequential ATPG
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal

34. BerkMin: A Fast and Robust Sat-Solver
Evgueni Goldberg, Yakov Novikov

35. Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-Chip Test Data Compression/Decompression
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici

36. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
P. Bernardi, E. Sánchez, M. Schillaci, G. Squillero, M. Sonza Reorda

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Keywords: TECHNOLOGY & ENGINEERING / General TEC000000