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Li, Yamin

Computer Principles and Design in Verilog HDL

Li, Yamin - Computer Principles and Design in Verilog HDL, ebook

139,50€

Ebook, ePUB with Adobe DRM
ISBN: 9781118841129
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Printing165 pages with an additional page accrued every 5 hours, capped at 165 pages
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Keywords: computer architecture, microprocessor design, industrially important Hardware Description Language (HDL), readily simulate, adjust the operation of each design, industrially relevant skills, computer principles, computer design, Verilog HDL (Hardware Description Language), implement design, computer fundamentals, performance evaluation, digital circuits, computer arithmetic algorithms, Wallace Tree for multiplication, Newton-Raphson algorithm, Goldschmidt algorithm for division and square root, instruction set architecture, ALU design, register file design, single-cycle CPU, multiple-cycle CPU, pipelined CPU designs, interrupts, exceptions, precise interrupts/exceptions, floating-point algorithms, FPU design, and pipelined CPU/FPU design in Verilog HDL, multithreading CPU design in Verilog HDL, memory, cache, virtual memory management, design of CPU/FPU with cache, TLB in Verilog HDL, Multi-core CPU design in Verilog HDL, UART (Universal Asynchronous Receiver Transmitter), PS/2 keyboard and mouse, VGA (Video Graphics Array), I2C series bus PCI, parallel bus interface design in Verilog HDL, high-performance computers, interconnection networks, Verilog HDL source codes, simulation waveforms, CAD/CAE tools, computer architecture, microprocessor design, industrially important Hardware Description Language (HDL), readily simulate, adjust the operation of each design, industrially relevant skills, computer principles, computer design, Verilog HDL (Hardware Description Language), implement design, computer fundamentals, performance evaluation, digital circuits, computer arithmetic algorithms, Wallace Tree for multiplication, Newton-Raphson algorithm, Goldschmidt algorithm for division and square root, instruction set architecture, ALU design, register file design, single-cycle CPU, multiple-cycle CPU, pipelined CPU designs, interrupts, exceptions, precise interrupts/exceptions, floating-point algorithms, FPU design, and pipelined CPU/FPU design in Verilog HDL, multithreading CPU design in Verilog HDL, memory, cache, virtual memory management, design of CPU/FPU with cache, TLB in Verilog HDL, Multi-core CPU design in Verilog HDL, UART (Universal Asynchronous Receiver Transmitter), PS/2 keyboard and mouse, VGA (Video Graphics Array), I2C series bus PCI, parallel bus interface design in Verilog HDL, high-performance computers, interconnection networks, Verilog HDL source codes, simulation waveforms, CAD/CAE tools, Circuit Theory & Design

Author(s)
Publisher
John Wiley and Sons, Inc.
Publication year
2015
Language
en
Edition
1
Page amount
550 pages
Category
Technology, Energy, Traffic
Format
Ebook
eISBN (ePUB)
9781118841129
Printed ISBN
9781118841099

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