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Jespers, Paul

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits

Jespers, Paul - The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits, ebook

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ISBN: 9780387471013
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Table of contents

1. Sizing the Intrinsic Gain Stage
Paul G. A. Jespers

2. The Charge Sheet Model Revisited
Paul G. A. Jespers

3. Graphical Interpretation of the Charge Sheet Model
Paul G. A. Jespers

4. Compact Modeling
Paul G. A. Jespers

5. The Real Transistor
Paul G. A. Jespers

6. The Real Intrinsic Gain Stage
Paul G. A. Jespers

7. The Common-Gate Configuration
Paul G. A. Jespers

8. Sizing the Miller Op. Amp.
Paul G. A. Jespers

Keywords: Engineering, Circuits and Systems, Processor Architectures, Solid State Physics, Spectroscopy and Microscopy

Author(s)
Publisher
Springer
Publication year
2010
Language
en
Edition
1
Series
Analog Circuits and Signal Processing
Category
Technology, Energy, Traffic
Format
Ebook
eISBN (PDF)
9780387471013

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