Reconfigurable Networks-on-Chip

1. Communication Centric Design
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

2. Preliminaries
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

3. Techniques for High Performance Noc Routing
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

4. Performance-Energy Tradeoffs for Noc Reliability
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

5. Energy-Aware Task Scheduling for Noc-Based DVS System
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

6. Bidirectional Noc Architecture
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

7. Quality-of-Service in BiNoc
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

8. Fault Tolerance in BiNoC
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

9. Energy-Aware Application Mapping for BiNoC
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

10. Concluding Remarks
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

Keywords: Engineering, Circuits and Systems, Processor Architectures