New Algorithms, Architectures and Applications for Reconfigurable Computing

1. Extra-dimensional Island-Style FPGAs
Herman Schmit

2. A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins

3. Stream-based XPP Architectures in Adaptive System-on-Chip Integration
Jürgen Becker, Martin Vorbach

4. Core-Based Architecture for Data Transfer Control in SoC Design
Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, José Luis Martín, Jaime Jiménez

5. Customizable and Reduced Hardware Motion Estimation Processors
Nuno Roma, Tiago Dias, Leonel Sousa

6. Enabling Run-time Task Relocation on Reconfigurable Systems
J-Y. Mignolet, V. Nollet, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins

7. A Unified Codesign Environment
Theerayod Wiangtong, Peter Y.K Cheung, Wayne Luk

8. Mapping Applications to a Coarse Grain Reconfigurable System
Yuanqing Guo, Gerard J.M. Smit, Michèl A.J. Rosien, Paul M. Heysters, Thijs Krol, Hajo Broersma

9. Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture
João M.P. Cardoso, Markus Weinhardt

10. Run-time Defragmentation for Dynamically Reconfigurable Hardware
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira

11. Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems
S. Lange, U. Kebschull

12. A Low Energy Data Management for Multi-Context Reconfigurable Architectures
M. Sanchez-Elez, M. Fernandez, R. Hermida, N. Bagherzadeh

13. Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study
Fernando Moraes, Ney Calazans, Leandro Möller, Eduardo Brião, Ewerson Carvalho

14. Design Flow for a Reconfigurable Processor
Alberto Rosa, Luciano Lavagno, Claudio Passerone

15. IPsec-Protected Transport of HDTV over IP
Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj

16. Fast, Large-scale String Match for a 10 Gbps FPGA-based NIDS
Ioannis Sourdis, Dionisios Pnevmatikatos

17. Architecture and FPGA Implementation of a Digit-serial RSA Processor
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese

18. Division in GF(p) for Application in Elliptic Curve Cryptosystems on Field Programmable Logic
Alan Daly, William Marnane, Tim Kerins, Emanuel Popovici

19. A New Arithmetic Unit in GF(2M) for Reconfigurable Hardware Implementation
Chang Hoon Kim, Chun Pyo Hong, Soonhak Kwon, Yun Ki Kwon

20. Performance Analysis of SHACAL-1 Encryption Hardware Architectures
Máire McLoone, J.V. McCanny

21. Security Aspects of FPGAs in Cryptographic Applications
Thomas Wollinger, Christof Paar

22. Bioinspired Stimulus Encoder for Cortical Visual Neuroprostheses
Leonel Sousa, Pedro Tomás, Francisco Pelayo, Antonio Martinez, Christian A. Morillas, Samuel Romero

23. A Smith-Waterman Systolic Cell
C.W. Yu, K.H. Kwong, K.H. Lee, P.H.W. Leong

24. The Effects of Polynomial Degrees
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y.K. Cheung

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Keywords: TECHNOLOGY & ENGINEERING / General TEC000000