SAT-Based Scalable Formal Verification Solutions

1. Design Verification Challenges
2. Background
Part I.Basic Infrastructure

3. Efficient Boolean Representation
4. Hybrid DPLL-Style SAT Solver
Part II.Falsification

5. SAT-Based Bounded Model Checking
6. Distributed SAT-Based BMC
7. Efficient Memory Modeling in BMC
8. BMC for Multi-Clock Systems
Part III.Proof Methods

9. Proof by Induction
10. Unbounded Model Checking
Part IV.Abstraction/Refinement

11. Proof-Based Iterative Abstraction
Part V.Verification Procedure

12. SAT-Based Verification Framework
13. Synthesis for Verification

DRM-restrictions

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Keywords: COMPUTERS / Computer Science COM014000